1. Field of the Invention
The present invention relates to a multi-layered resist structure and a manufacturing method of a semiconductor device and, more particularly, a multi-layered resist structure employed to pattern the film and a manufacturing method of a semiconductor device comprising the patterning steps employing such multi-layered resist structure.
2. Description of the Prior Art
In the fabrication of the semiconductor device, there are contained the step of forming recess portions by patterning the silicon substrate, the step of forming electrodes by patterning the silicon film, etc. Such patterning is carried out by etching partially the silicon substrate, the silicon film, etc. while using the resist pattern as a mask.
However, since the resist pattern is formed to have a narrow width with the higher integration and the miniaturization of the semiconductor device, an aspect ratio that represents a ratio of a height to a width becomes large and then the resist pattern falls down, so that the pattern failure is ready to occur. Therefore, in order to reduce the aspect ratio, it is often tried that the resist pattern is formed thin. In this case, the thinning of the resist pattern has a limit with regard to the dry etching resistance.
For this reason, in order to prevent the falling-down of the resist pattern, it is effective to form the resist pattern as a triple-layered structure. The triple-layered structure of the resist pattern consists of a lower resist layer, an intermediate layer, and an upper resist layer. The intermediate layer is formed of the material that is different from the lower and upper resist layers.
For example, it is set forth in Patent Application Publication (KOKAI) Hei 3-126036 that the triple-layered structure constructed by putting the silylation product such as the serpentine, or the like between the resists for the g-line (wavelength 436 nm) exposure is employed. Also, the triple-layered structure in which the alkoxysilane/acrylic resin copolymer or SOG is employed as the intermediate layer and the DUV exposure material is employed as the upper resist layer is set forth in Patent Application Publication (KOKAI) Hei 5-94022. In addition, the triple-layered structure in which the amorphous silicon is employed as the intermediate layer and the X-ray exposure material is employed as the upper resist layer is set forth in Patent Application Publication (KOKAI) Hei 5-121312.
These resists of the triple-layered structure are patterned via steps of exposing/developing the upper resist layer to pattern it and then dry-etching the intermediate layer and the lower resist layer while using the pattern of the upper resist layer as a mask. Sometimes the upper resist layer is removed by the dry etching.
Also, the triple-layered structure in which the novolak type photoresist is employed as the lower resist layer, the silicon-containing negative type resist such as polyallylsilsesquioxane is employed as the intermediate layer, and the negative type resist is employed as the upper resist layer is set forth in Patent Application Publication (KOKAI) Hei 5-36599. In this case, the upper resist layer is patterned by exposing it by the DUV light and then developing it, then the intermediate layer is exposed by the ArF excimer laser while using the upper resist layer as a mask and then developed to form the pattern of the intermediate layer and remove the upper resist layer, and then the lower resist layer is dry-etched while using the intermediate layer as a mask, whereby the silicon-pattern forming mask is formed. Here the DUV light is a light having a wavelength of 230 to 300 nm.
Then, in order to miniaturize further the silicon pattern constituting the semiconductor device, the alicyclic resin that is exposed to the ArF excimer laser having a wavelength of 193 nm is employed as the upper resist layer of the triple-layered structure and also the SOG (Spin-On-Glass) is employed as the intermediate layer of the triple-layered structure. At that time, based on the experiment made by the inventors of the present invention, it becomes apparent that the deformation of the pattern of the upper resist layer easily occurs.
It may be considered as the cause of such deformation of the upper resist layer that the etching resistance of the material per se of the upper resist layer is not good in etching the intermediate layer and that the adhesiveness of the upper resist layer to the intermediate layer is not good.